1×16 DEMULTIPLEXER

Interactive Data Distribution & Hierarchical Circuit Simulation

1 Data Input • 4 Select Lines • 16 Outputs
Control Panel MANUAL MODE
Data Input (D) LOGIC 1
Select Lines (S3 S2 S1 S0) 0000 (DEC: 0)
Quick Select Presets
Auto Demonstration Sequential Cycle
Routing Speed: 1.0s
Selected Output Monitor
Y0
OUTPUT Y0 = 1
Select Binary 0000
Data Input (D) 1
Minterm Equation m0
Other Outputs ALL LOW (0)
Routing Pipeline & State Monitor ACTIVE PATH
INPUT RECEIVED STAGE 1 — S3 STAGE 2 — S2 STAGE 3 — S1 STAGE 4 — S0 FINAL OUTPUT Y0
ROUTING TO Y0
Select value 0000 routes input data signal D to output Y0.
Hierarchical 1×16 DEMUX Circuit (4 Stages: 1 → 2 → 4 → 8 → 16)
Logic HIGH (1)
Selected Path
Logic LOW (0)
Input Stage Data Signal D Stage 1 — S3 1 DEMUX Stage 2 — S2 2 DEMUXES Stage 3 — S1 4 DEMUXES Stage 4 — S0 8 DEMUXES 16 Outputs Y0 – Y15 S3 S2 S1 S0 D 1×2 DEMUX Stage 1 (S3) A0 A1 1×2 DEMUX Stage 2.0 1×2 DEMUX Stage 2.1 B0 B1 B2 B3 1×2 DEMUXStage 3.0 1×2 DEMUXStage 3.1 1×2 DEMUXStage 3.2 1×2 DEMUXStage 3.3 C0 C1 C2 C3 C4 C5 C6 C7 STG 4.0 STG 4.1 STG 4.2 STG 4.3 STG 4.4 STG 4.5 STG 4.6 STG 4.7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

16-Bit Output Vector Display

MSB: Y15  ←  BIT ORDERING  →  LSB: Y0
Output Bank Indicators (Y0 to Y15) Selected Output = D • All Others = 0
Complete 1×16 Demultiplexer Selection & Truth Table Click any row to select output
DEC S3 S2 S1 S0 Selected Output Product Term Equation Output State (D=1)
What is a 1×16 Demultiplexer? Theory

A Demultiplexer (DEMUX) is a digital combinational logic circuit that takes a single input data signal (D) and routes it to one of multiple outputs depending on the state of select lines.

In a 1×16 DEMUX, four select lines (S3, S2, S1, S0) route data input D to one of sixteen outputs (Y0 through Y15):

Outputs = 24 = 16

The selected output receives signal D, while all 15 unselected output lines remain LOW (0).

Hierarchical Tree Architecture 1 → 2 → 4 → 8

The 1×16 DEMUX is constructed using 15 smaller 1×2 DEMUX blocks across four stages:

  • Stage 1 (S3): 1 DEMUX splits input D into A0, A1.
  • Stage 2 (S2): 2 DEMUXes split A0, A1 into B0, B1, B2, B3.
  • Stage 3 (S1): 4 DEMUXes split B0..B3 into C0..C7.
  • Stage 4 (S0): 8 DEMUXes split C0..C7 into final outputs Y0..Y15.
Total 1×2 Blocks = 1 + 2 + 4 + 8 = 15
MUX vs DEMUX Comparison Architecture
Property Multiplexer (MUX) Demultiplexer (DEMUX)
Signal Path Many Inputs → One Output One Input → Many Outputs
Primary Function Data Selector Data Distributor
Select Line Formula N = log2(Inputs) N = log2(Outputs)
Applications Practical Use
  • Serial-to-Parallel Conversion: Distributing serial stream to 16 parallel channels.
  • RAM / ROM Chip Selection: Decoding 4-bit memory addresses to enable specific chips.
  • Data Routing Networks: Switching single channel sensor feeds to 16 test destinations.